diff -urbN a/arch/arm/dts/am4372.dtsi b/arch/arm/dts/am4372.dtsi
--- a/arch/arm/dts/am4372.dtsi	2018-12-16 09:28:19.000000000 +0300
+++ b/arch/arm/dts/am4372.dtsi	2019-01-09 14:59:20.669270699 +0300
@@ -764,7 +764,8 @@
 			reg = <0x48038000 0x2000>,
 			      <0x46000000 0x400000>;
 			reg-names = "mpu", "dat";
-			interrupts = <80>, <81>;
+                        interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "tx", "rx";
 			status = "disabled";
 			dmas = <&edma 8>,
@@ -778,7 +779,8 @@
 			reg = <0x4803C000 0x2000>,
 			      <0x46400000 0x400000>;
 			reg-names = "mpu", "dat";
-			interrupts = <82>, <83>;
+                        interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "tx", "rx";
 			status = "disabled";
 			dmas = <&edma 10>,
@@ -807,6 +809,8 @@
 			gpmc,num-waitpins = <2>;
 			#address-cells = <2>;
 			#size-cells = <1>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
 			status = "disabled";
 		};
 
diff -urbN a/arch/arm/dts/am437x-usomiq.dts b/arch/arm/dts/am437x-usomiq.dts
--- a/arch/arm/dts/am437x-usomiq.dts	1970-01-01 03:00:00.000000000 +0300
+++ b/arch/arm/dts/am437x-usomiq.dts	2019-01-22 11:54:58.634217819 +0300
@@ -0,0 +1,454 @@
+/*
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/* AM437x GP EVM */
+
+/dts-v1/;
+
+#include "am4372.dtsi"
+#include <dt-bindings/pinctrl/am43xx.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	model = "MENTOREL AM437x uSomIQ";
+	compatible = "ti,am437x-usomiq","ti,am4372","ti,am43";
+
+	chosen {
+		stdout-path = &uart0;
+		tick-timer = &timer2;
+	};
+
+	vmmcsd_fixed: fixedregulator-sd {
+		compatible = "regulator-fixed";
+		regulator-name = "vmmcsd_fixed";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		enable-active-high;
+	};
+
+	vmmcwl_fixed: fixedregulator-mmcwl {
+		compatible = "regulator-fixed";
+		regulator-name = "vmmcwl_fixed";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		gpio = <&gpio1 20 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	/* fixed 12MHz oscillator */
+	refclk: oscillator {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <12000000>;
+	};
+
+};
+
+&am43xx_pinmux {
+	i2c0_pins: i2c0_pins {
+		pinctrl-single,pins = <
+			0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)  /* i2c0_sda.i2c0_sda */
+			0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)  /* i2c0_scl.i2c0_scl */
+		>;
+	};
+
+	i2c1_pins: i2c1_pins {
+		pinctrl-single,pins = <
+			0x15c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2)  /* spi0_cs0.i2c1_scl */
+			0x158 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2)  /* spi0_d1.i2c1_sda  */
+		>;
+	};
+
+	mmc1_pins: pinmux_mmc1_pins {
+		pinctrl-single,pins = <
+			0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
+		>;
+	};
+
+	cpsw_default: cpsw_default {
+		pinctrl-single,pins = <
+			/* Slave 1 */
+			0x110 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mii1_rxerr.mii1_rxerr */
+			0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mii1_txen.mii1_txen */
+			0x118 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mii1_rxdv.mii1_rxdv */
+			0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mii1_txd3.mii1_txd3 */
+			0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mii1_txd2.mii1_txd2 */
+			0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mii1_txd1.mii1_txd1 */
+			0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mii1_txd0.mii1_txd0 */
+			0x12c (PIN_INPUT_PULLUP | MUX_MODE0)	/* mii1_txclk.mii1_txclk */
+			0x130 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mii1_rxclk.mii1_rxclk */
+			0x134 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mii1_rxd3.mii1_rxd3 */
+			0x138 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mii1_rxd2.mii1_rxd2 */
+			0x13c (PIN_INPUT_PULLUP | MUX_MODE0)	/* mii1_rxd1.mii1_rxd1 */
+			0x140 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mii1_rxd0.mii1_rxd0 */
+		>;
+	};
+
+	cpsw_sleep: cpsw_sleep {
+		pinctrl-single,pins = <
+			/* Slave 1 reset value */
+			0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+		>;
+	};
+
+	davinci_mdio_default: davinci_mdio_default {
+		pinctrl-single,pins = <
+			/* MDIO */
+			0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)	/* mdio_data.mdio_data */
+			0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0)			/* mdio_clk.mdio_clk */
+		>;
+	};
+
+	davinci_mdio_sleep: davinci_mdio_sleep {
+		pinctrl-single,pins = <
+			/* MDIO reset value */
+			0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+		>;
+	};
+
+	nandflash_pins_s0: nandflash_pins_s0 {
+		pinctrl-single,pins = <
+			0x0  (PIN_INPUT  | MUX_MODE0)	/* gpmc_ad0.gpmc_ad0 */
+			0x4  (PIN_INPUT  | MUX_MODE0)	/* gpmc_ad1.gpmc_ad1 */
+			0x8  (PIN_INPUT  | MUX_MODE0)	/* gpmc_ad2.gpmc_ad2 */
+			0xc  (PIN_INPUT  | MUX_MODE0)	/* gpmc_ad3.gpmc_ad3 */
+			0x10 (PIN_INPUT  | MUX_MODE0)	/* gpmc_ad4.gpmc_ad4 */
+			0x14 (PIN_INPUT  | MUX_MODE0)	/* gpmc_ad5.gpmc_ad5 */
+			0x18 (PIN_INPUT  | MUX_MODE0)	/* gpmc_ad6.gpmc_ad6 */
+			0x1c (PIN_INPUT  | MUX_MODE0)	/* gpmc_ad7.gpmc_ad7 */
+			0x70 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_wait0.gpmc_wait0 */
+			0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7)	/* gpmc_wpn.gpmc_wpn */
+			0x7c (PIN_OUTPUT | MUX_MODE0)		/* gpmc_csn0.gpmc_csn0  */
+			0x90 (PIN_OUTPUT | MUX_MODE0)		/* gpmc_advn_ale.gpmc_advn_ale */
+			0x94 (PIN_OUTPUT | MUX_MODE0)		/* gpmc_oen_ren.gpmc_oen_ren */
+			0x98 (PIN_OUTPUT | MUX_MODE0)		/* gpmc_wen.gpmc_wen */
+			0x9c (PIN_OUTPUT | MUX_MODE0)		/* gpmc_be0n_cle.gpmc_be0n_cle */
+		>;
+	};
+
+	qspi_pins_default: qspi_pins_default {
+		pinctrl-single,pins = <
+			0x210 (PIN_OUTPUT | MUX_MODE3)  /* cam0_data2.qspi_clk*/
+			0x214 (PIN_OUTPUT_PULLUP | MUX_MODE3) /* cam0_data3.qspi_csn */
+			0x218 (PIN_INPUT_PULLUP | MUX_MODE3)  /* cam0_data4.qspi_d0 */
+			0x21C (PIN_INPUT_PULLUP | MUX_MODE3)  /* cam0_data5.qspi_d1 */
+			0x220 (PIN_INPUT_PULLUP | MUX_MODE3)  /* cam0_data6.qspi_d2 */
+			0x224 (PIN_INPUT_PULLUP | MUX_MODE3)  /* cam0_data7.qspi_d3 */
+		>;
+	};
+
+	qspi_pins_sleep: qspi_pins_sleep {
+		pinctrl-single,pins = <
+			0x210 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x214 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x218 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x21C (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x220 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x224 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+		>;
+	};
+};
+
+&i2c0 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c0_pins>;
+	clock-frequency = <100000>;
+
+	tps65218: tps65218@24 {
+		reg = <0x24>;
+		compatible = "ti,tps65218";
+		interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */
+		interrupt-controller;
+		#interrupt-cells = <2>;
+
+		dcdc1: regulator-dcdc1 {
+			compatible = "ti,tps65218-dcdc1";
+			regulator-name = "vdd_core";
+			regulator-min-microvolt = <912000>;
+			regulator-max-microvolt = <1144000>;
+			regulator-boot-on;
+			regulator-always-on;
+		};
+
+		dcdc2: regulator-dcdc2 {
+			compatible = "ti,tps65218-dcdc2";
+			regulator-name = "vdd_mpu";
+			regulator-min-microvolt = <912000>;
+			regulator-max-microvolt = <1378000>;
+			regulator-boot-on;
+			regulator-always-on;
+		};
+
+		dcdc3: regulator-dcdc3 {
+			compatible = "ti,tps65218-dcdc3";
+			regulator-name = "vdcdc3";
+			regulator-min-microvolt = <1500000>;
+			regulator-max-microvolt = <1500000>;
+			regulator-boot-on;
+			regulator-always-on;
+		};
+		dcdc5: regulator-dcdc5 {
+			compatible = "ti,tps65218-dcdc5";
+			regulator-name = "v1_0bat";
+			regulator-min-microvolt = <1000000>;
+			regulator-max-microvolt = <1000000>;
+		};
+
+		dcdc6: regulator-dcdc6 {
+			compatible = "ti,tps65218-dcdc6";
+			regulator-name = "v1_8bat";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+		};
+
+		ldo1: regulator-ldo1 {
+			compatible = "ti,tps65218-ldo1";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-boot-on;
+			regulator-always-on;
+		};
+	};
+};
+
+&i2c1 {
+	status = "okay";
+	pinctrl-0 = <&i2c1_pins>;
+};
+
+&epwmss0 {
+	status = "okay";
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio3 {
+	status = "okay";
+};
+
+&gpio4 {
+	status = "okay";
+};
+
+&gpio5 {
+	status = "okay";
+	ti,no-reset-on-init;
+};
+
+&mmc1 {
+	status = "okay";
+	vmmc-supply = <&vmmcsd_fixed>;
+	bus-width = <4>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc1_pins>;
+	cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
+};
+
+&qspi {
+	status = "okay";
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&qspi_pins_default>;
+	pinctrl-1 = <&qspi_pins_sleep>;
+
+	spi-max-frequency = <48000000>;
+	m25p80@0 {
+		compatible = "mx66l51235l", "spi-flash";
+		spi-max-frequency = <48000000>;
+		reg = <0>;
+		spi-cpol;
+		spi-cpha;
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <4>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		/*
+		 * MTD partition table.  The ROM checks the first 512KiB for a
+		 * valid file to boot(XIP).
+		 */
+		partition@0 {
+			label = "QSPI.U_BOOT";
+			reg = <0x00000000 0x000080000>;
+		};
+		partition@1 {
+			label = "QSPI.U_BOOT.backup";
+			reg = <0x00080000 0x00080000>;
+		};
+		partition@2 {
+			label = "QSPI.U-BOOT-SPL_OS";
+			reg = <0x00100000 0x00010000>;
+		};
+		partition@3 {
+			label = "QSPI.U_BOOT_ENV";
+			reg = <0x00110000 0x00010000>;
+		};
+		partition@4 {
+			label = "QSPI.U-BOOT-ENV.backup";
+			reg = <0x00120000 0x00010000>;
+		};
+		partition@5 {
+			label = "QSPI.KERNEL";
+			reg = <0x00130000 0x0800000>;
+		};
+		partition@6 {
+			label = "QSPI.FILESYSTEM";
+			reg = <0x00930000 0x36D0000>;
+		};
+	};
+};
+
+&edma {
+	ti,edma-xbar-event-map = /bits/ 16 <1 30
+					    2 31>;
+};
+
+&usb2_phy1 {
+	status = "okay";
+};
+
+&usb1 {
+	dr_mode = "peripheral";
+	status = "okay";
+};
+
+&usb2_phy2 {
+	status = "okay";
+};
+
+&usb2 {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&mac {
+	slaves = <1>;
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&cpsw_default>;
+	pinctrl-1 = <&cpsw_sleep>;
+	status = "okay";
+};
+
+&davinci_mdio {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&davinci_mdio_default>;
+	pinctrl-1 = <&davinci_mdio_sleep>;
+	status = "okay";
+};
+
+&cpsw_emac0 {
+	phy_id = <&davinci_mdio>, <0>;
+	phy-mode = "mii";
+};
+
+&elm {
+	status = "okay";
+};
+
+&gpmc {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&nandflash_pins_s0>;
+	ranges = <0 0 0x08000000 0x1000000>;	/* CS0: 16MB for NAND */
+	nand@0,0 {
+		reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
+		ti,nand-ecc-opt = "bch8";
+		ti,elm-id = <&elm>;
+		nand-bus-width = <8>;
+		gpmc,device-width = <1>;
+		gpmc,sync-clk-ps = <0>;
+		gpmc,cs-on-ns = <0>;
+		gpmc,cs-rd-off-ns = <44>;
+		gpmc,cs-wr-off-ns = <44>;
+		gpmc,adv-on-ns = <6>;
+		gpmc,adv-rd-off-ns = <34>;
+		gpmc,adv-wr-off-ns = <44>;
+		gpmc,we-on-ns = <0>;
+		gpmc,we-off-ns = <40>;
+		gpmc,oe-on-ns = <0>;
+		gpmc,oe-off-ns = <54>;
+		gpmc,access-ns = <64>;
+		gpmc,rd-cycle-ns = <82>;
+		gpmc,wr-cycle-ns = <82>;
+		gpmc,wait-on-read = "true";
+		gpmc,wait-on-write = "true";
+		gpmc,bus-turnaround-ns = <0>;
+		gpmc,cycle2cycle-delay-ns = <0>;
+		gpmc,clk-activation-ns = <0>;
+		gpmc,wait-monitoring-ns = <0>;
+		gpmc,wr-access-ns = <40>;
+		gpmc,wr-data-mux-bus-ns = <0>;
+		/* MTD partition table */
+		/* All SPL-* partitions are sized to minimal length
+		 * which can be independently programmable. For
+		 * NAND flash this is equal to size of erase-block */
+		#address-cells = <1>;
+		#size-cells = <1>;
+		partition@0 {
+			label = "NAND.SPL";
+			reg = <0x00000000 0x000020000>;
+		};
+		partition@1 {
+			label = "NAND.SPL.backup1";
+			reg = <0x00020000 0x00020000>;
+		};
+		partition@2 {
+			label = "NAND.SPL.backup2";
+			reg = <0x00040000 0x00020000>;
+		};
+		partition@3 {
+			label = "NAND.SPL.backup3";
+			reg = <0x00060000 0x00020000>;
+		};
+		partition@4 {
+			label = "NAND.u-boot-spl-os";
+			reg = <0x00080000 0x00040000>;
+		};
+		partition@5 {
+			label = "NAND.u-boot";
+			reg = <0x000C0000 0x00100000>;
+		};
+		partition@6 {
+			label = "NAND.u-boot-env";
+			reg = <0x001C0000 0x00020000>;
+		};
+		partition@7 {
+			label = "NAND.u-boot-env.backup1";
+			reg = <0x001E0000 0x00020000>;
+		};
+		partition@8 {
+			label = "NAND.kernel";
+			reg = <0x00200000 0x00800000>;
+		};
+		partition@9 {
+			label = "NAND.file-system";
+			reg = <0x00A00000 0x0F600000>;
+		};
+	};
+};
+
diff -urbN a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
--- a/arch/arm/dts/Makefile	2018-12-16 09:28:19.000000000 +0300
+++ b/arch/arm/dts/Makefile	2019-05-24 15:38:56.573722812 +0300
@@ -164,7 +164,8 @@
 	am335x-rut.dtb
 dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb	\
 	am43x-epos-evm.dtb \
-	am437x-idk-evm.dtb
+	am437x-idk-evm.dtb \
+	am437x-usomiq.dtb 
 dtb-$(CONFIG_TI816X) += dm8168-evm.dtb
 dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb
 
diff -urbN a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
--- a/board/ti/am43xx/board.c	2018-12-16 09:28:21.000000000 +0300
+++ b/board/ti/am43xx/board.c	2019-05-24 15:41:04.053939365 +0300
@@ -184,6 +184,17 @@
 	.emif_sdram_config_ext	= 0xc163,
 };
 
+const struct ctrl_ioregs ioregs_ddr3_16 = {
+	.cm0ioctl		= DDR3_ADDRCTRL_IOCTRL_VALUE,
+	.cm1ioctl		= DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
+	.cm2ioctl		= DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,
+	.dt0ioctl		= DDR3_DATA0_IOCTRL_VALUE,
+	.dt1ioctl		= DDR3_DATA0_IOCTRL_VALUE,
+	.dt2ioctrl		= DDR3_DATA0_IOCTRL_VALUE,
+	.dt3ioctrl		= DDR3_DATA0_IOCTRL_VALUE,
+	.emif_sdram_config_ext	= 0xc163|(1<<17), /*uSomIQ uses 16-bit DDR3*/
+};
+
 const struct emif_regs ddr3_emif_regs_400Mhz = {
 	.sdram_config			= 0x638413B2,
 	.ref_ctrl			= 0x00000C30,
@@ -307,6 +318,31 @@
 	.emif_cos_config		= 0x00ffffff
 };
 
+const struct emif_regs ddr3_usom_emif_regs_400Mhz = {
+	.sdram_config			= 0x638413B2|(1<<14),/*uSomIQ uses 16-bit DDR3*/
+	.ref_ctrl			= 0x00000C30,
+	.sdram_tim1			= 0xEAAAD4DB,
+	.sdram_tim2			= 0x266B7FDA,
+	.sdram_tim3			= 0x107F8678,
+	.read_idle_ctrl			= 0x00050000,
+	.zq_config			= 0x50074BE4,
+	.temp_alert_config		= 0x0,
+	.emif_ddr_phy_ctlr_1		= 0x0E004008,
+	.emif_ddr_ext_phy_ctrl_1	= 0x08020080,
+	.emif_ddr_ext_phy_ctrl_2	= 0x00400040,
+	.emif_ddr_ext_phy_ctrl_3	= 0x00400040,
+	.emif_ddr_ext_phy_ctrl_4	= 0x00400040,
+	.emif_ddr_ext_phy_ctrl_5	= 0x00400040,
+	.emif_rd_wr_lvl_rmp_win		= 0x0,
+	.emif_rd_wr_lvl_rmp_ctl		= 0x0,
+	.emif_rd_wr_lvl_ctl		= 0x0,
+	.emif_rd_wr_exec_thresh		= 0x80000405,
+	.emif_prio_class_serv_map	= 0x80000001,
+	.emif_connect_id_serv_1_map	= 0x80000094,
+	.emif_connect_id_serv_2_map	= 0x00000000,
+	.emif_cos_config		= 0x000FFFFF
+};
+
 void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
 {
 	if (board_is_eposevm()) {
@@ -323,7 +359,7 @@
 
 	if (board_is_eposevm())
 		return &epos_evm_dpll_ddr[ind];
-	else if (board_is_evm() || board_is_sk())
+	else if (board_is_evm() || board_is_sk() || board_is_me_usom())
 		return &gp_evm_dpll_ddr;
 	else if (board_is_idk())
 		return &idk_dpll_ddr;
@@ -530,6 +566,7 @@
 	RTC_BOARD_EVM12,
 	RTC_BOARD_GPEVM,
 	RTC_BOARD_SK,
+        RTC_BOARD_USOM,
 };
 
 /*
@@ -560,6 +597,9 @@
 	case RTC_BOARD_SK:
 		name = "AM43__SK";
 		break;
+        case RTC_BOARD_USOM:
+		name = "AM43USOM";
+		break;
 	}
 	ti_i2c_eeprom_am_set(name, rev);
 }
@@ -576,6 +616,8 @@
 		return RTC_BOARD_GPEVM;
 	else if (board_is_sk())
 		return RTC_BOARD_SK;
+	else if (board_is_me_usom())
+		return RTC_BOARD_USOM;
 
 	return 0;
 }
@@ -607,6 +649,12 @@
 	} else if (board_is_idk()) {
 		config_ddr(400, &ioregs_ddr3, NULL, NULL,
 			   &ddr3_idk_emif_regs_400Mhz, 0);
+	} else if (board_is_me_usom()) {
+		config_ddr(400, &ioregs_ddr3_16, NULL, NULL,
+			   &ddr3_usom_emif_regs_400Mhz, 0);
+        } else { /* No EEPROM - Consider it is uSomIQ */
+		config_ddr(400, &ioregs_ddr3_16, NULL, NULL,
+			   &ddr3_usom_emif_regs_400Mhz, 0);
 	}
 }
 #endif
@@ -909,6 +957,10 @@
 		writel(RGMII_MODE_ENABLE, &cdev->miisel);
 		cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
 		cpsw_slaves[0].phy_addr = 0;
+	} else if (board_is_me_usom()) {
+                writel(MII_MODE_ENABLE, &cdev->miisel);
+                cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_MII;
+		cpsw_slaves[0].phy_addr = 0;
 	} else {
 		writel(RGMII_MODE_ENABLE, &cdev->miisel);
 		cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
@@ -956,6 +1008,8 @@
 		return 0;
 	else if (board_is_idk() && !strcmp(name, "am437x-idk-evm"))
 		return 0;
+	else if (board_is_me_usom() && !strcmp(name, "am437x-usomiq"))
+		return 0;
 	else
 		return -1;
 }
diff -urbN a/board/ti/am43xx/board.h b/board/ti/am43xx/board.h
--- a/board/ti/am43xx/board.h	2018-12-16 09:28:21.000000000 +0300
+++ b/board/ti/am43xx/board.h	2019-05-24 15:39:35.116579122 +0300
@@ -57,6 +57,11 @@
 	return board_is_evm() && strncmp("1.2", board_ti_get_rev(), 3) <= 0;
 }
 
+static inline int board_is_me_usom(void)
+{
+	return board_ti_is("AM43USOM");
+}
+
 void enable_uart0_pin_mux(void);
 void enable_board_pin_mux(void);
 void enable_i2c0_pin_mux(void);
diff -urbN a/board/ti/am43xx/MAINTAINERS b/board/ti/am43xx/MAINTAINERS
--- a/board/ti/am43xx/MAINTAINERS	2018-12-16 09:28:21.000000000 +0300
+++ b/board/ti/am43xx/MAINTAINERS	2019-01-09 14:30:35.373832827 +0300
@@ -9,3 +9,6 @@
 F:	configs/am43xx_evm_usbhost_boot_defconfig
 F:	configs/am43xx_evm_rtconly_defconfig
 F:	configs/am43xx_hs_evm_defconfig
+F:	configs/am43xx_evm_usomiq_defconfig
+F:	configs/am43xx_evm_usomiq_nand4k_defconfig
+F:	configs/am43xx_evm_spider_defconfig
diff -urbN a/board/ti/am43xx/mux.c b/board/ti/am43xx/mux.c
--- a/board/ti/am43xx/mux.c	2018-12-16 09:28:21.000000000 +0300
+++ b/board/ti/am43xx/mux.c	2019-05-24 15:42:03.620170903 +0300
@@ -13,15 +13,26 @@
 #include "board.h"
 
 static struct module_pin_mux rmii1_pin_mux[] = {
-	{OFFSET(mii1_txen), MODE(1)},			/* RMII1_TXEN */
-	{OFFSET(mii1_txd1), MODE(1)},			/* RMII1_TD1 */
-	{OFFSET(mii1_txd0), MODE(1)},			/* RMII1_TD0 */
-	{OFFSET(mii1_rxd1), MODE(1) | RXACTIVE},	/* RMII1_RD1 */
-	{OFFSET(mii1_rxd0), MODE(1) | RXACTIVE},	/* RMII1_RD0 */
-	{OFFSET(mii1_rxdv), MODE(1) | RXACTIVE},	/* RMII1_RXDV */
-	{OFFSET(mii1_crs), MODE(1) | RXACTIVE},		/* RMII1_CRS_DV */
+	{OFFSET(mii1_crs), MODE(1) | RXACTIVE},		/* RMII1_CRS */
 	{OFFSET(mii1_rxerr), MODE(1) | RXACTIVE},	/* RMII1_RXERR */
-	{OFFSET(rmii1_refclk), MODE(0) | RXACTIVE},	/* RMII1_refclk */
+	{OFFSET(mii1_txen), MODE(1)},			/* RMII1_TXEN */
+	{OFFSET(mii1_txd1), MODE(1)},			/* RMII1_TXD1 */
+	{OFFSET(mii1_txd0), MODE(1)},			/* RMII1_TXD0 */
+	{OFFSET(mii1_rxd1), MODE(1) | RXACTIVE},	/* RMII1_RXD1 */
+	{OFFSET(mii1_rxd0), MODE(1) | RXACTIVE},	/* RMII1_RXD0 */
+	{OFFSET(rmii1_refclk), MODE(0) | RXACTIVE},	/* RMII1_REFCLK */
+	{-1},
+};
+
+static struct module_pin_mux rmii2_pin_mux[] = {
+	{OFFSET(gpmc_wait0), MODE(1) | RXACTIVE},	/* RMII2_CRS */
+	{OFFSET(gpmc_wpn), MODE(1) | RXACTIVE},	        /* RMII2_RXERR */
+	{OFFSET(gpmc_a0), MODE(1)},			/* RMII2_TXEN */
+	{OFFSET(gpmc_a4), MODE(1)},			/* RMII2_TXD1 */
+	{OFFSET(gpmc_a5), MODE(1)},			/* RMII2_TXD0 */
+	{OFFSET(gpmc_a10), MODE(1) | RXACTIVE},	        /* RMII2_RXD1 */
+	{OFFSET(gpmc_a11), MODE(1) | RXACTIVE},	        /* RMII2_RXD0 */
+	{OFFSET(mii1_col), MODE(1) | RXACTIVE},	        /* RMII2_REFCLK */
 	{-1},
 };
 
@@ -41,6 +52,23 @@
 	{-1},
 };
 
+static struct module_pin_mux mii1_pin_mux[] = {
+	{OFFSET(mii1_rxerr), MODE(0) | RXACTIVE},	/* MII1_RXERR */
+	{OFFSET(mii1_txen), MODE(0)},			/* MII1_TXEN */
+	{OFFSET(mii1_rxdv), MODE(0) | RXACTIVE},	/* MII1_RXDV */
+	{OFFSET(mii1_txd3), MODE(0)},			/* MII1_TXD3 */
+	{OFFSET(mii1_txd2), MODE(0)},			/* MII1_TXD2 */
+	{OFFSET(mii1_txd1), MODE(0)},			/* MII1_TXD1 */
+	{OFFSET(mii1_txd0), MODE(0)},			/* MII1_TXD0 */
+	{OFFSET(mii1_txclk), MODE(0) | RXACTIVE},	/* MII1_TXCLK */
+	{OFFSET(mii1_rxclk), MODE(0) | RXACTIVE},	/* MII1_RXCLK */
+	{OFFSET(mii1_rxd3), MODE(0) | RXACTIVE},	/* MII1_RXD3 */
+	{OFFSET(mii1_rxd2), MODE(0) | RXACTIVE},	/* MII1_RXD2 */
+	{OFFSET(mii1_rxd1), MODE(0) | RXACTIVE},	/* MII1_RXD1 */
+	{OFFSET(mii1_rxd0), MODE(0) | RXACTIVE},	/* MII1_RXD0 */
+	{-1},
+};
+
 static struct module_pin_mux mdio_pin_mux[] = {
 	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
 	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},	/* MDIO_CLK */
@@ -63,6 +91,21 @@
 	{-1},
 };
 
+static struct module_pin_mux mmc1_pin_mux[] = {
+	{OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT0 */
+	{OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT1 */
+	{OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT2 */
+	{OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT3 */
+	{OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT4 */
+	{OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT5 */
+	{OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT6 */
+	{OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT7 */
+	{OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)},	/* MMC1_CLK */
+	{OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)},	/* MMC1_CMD */
+	{OFFSET(cam0_data0), (MODE(7) | RXACTIVE | PULLUP_EN)},	/* MMC1_WP */
+	{-1},
+};
+
 static struct module_pin_mux i2c0_pin_mux[] = {
 	{OFFSET(i2c0_sda), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
 	{OFFSET(i2c0_scl), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
@@ -106,12 +149,12 @@
 #endif
 
 static __maybe_unused struct module_pin_mux qspi_pin_mux[] = {
-	{OFFSET(gpmc_csn0), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_CS0 */
-	{OFFSET(gpmc_csn3), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* QSPI_CLK */
-	{OFFSET(gpmc_advn_ale), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D0 */
-	{OFFSET(gpmc_oen_ren), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D1 */
-	{OFFSET(gpmc_wen), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D2 */
-	{OFFSET(gpmc_be0n_cle), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D3 */
+	{OFFSET(cam0_data3), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_CS0 */
+	{OFFSET(cam0_data2), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_CLK */
+	{OFFSET(cam0_data4), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D0 */
+	{OFFSET(cam0_data5), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D1 */
+	{OFFSET(cam0_data6), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D2 */
+	{OFFSET(cam0_data7), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D3 */
 	{-1},
 };
 
@@ -145,6 +188,12 @@
 #else
 		configure_module_pin_mux(qspi_pin_mux);
 #endif
+	} else if (board_is_me_usom()) {
+                configure_module_pin_mux(mii1_pin_mux);
+#if defined(CONFIG_NAND)
+                configure_module_pin_mux(nand_pin_mux);
+#endif
+		configure_module_pin_mux(qspi_pin_mux);
 	}
 }
 
diff -urbN a/board/ti/common/board_detect.c b/board/ti/common/board_detect.c
--- a/board/ti/common/board_detect.c	2018-12-16 09:28:21.000000000 +0300
+++ b/board/ti/common/board_detect.c	2019-05-28 13:43:16.371622589 +0300
@@ -269,8 +269,11 @@
 
 	rc = ti_i2c_eeprom_get(bus_addr, dev_addr, TI_EEPROM_HEADER_MAGIC,
 			       sizeof(am_ep), (uint8_t *)&am_ep);
-	if (rc)
-		return rc;
+	if (rc) {
+                /* Anyway run u-boot on empty EEPROM */
+                am_ep.header = TI_EEPROM_HEADER_MAGIC;
+                strlcpy(am_ep.name, "AM43USOM", TI_EEPROM_HDR_NAME_LEN + 1);
+        }
 
 	ep->header = am_ep.header;
 	strlcpy(ep->name, am_ep.name, TI_EEPROM_HDR_NAME_LEN + 1);
diff -urbN a/configs/am43xx_evm_usomiq_defconfig b/configs/am43xx_evm_usomiq_defconfig
--- a/configs/am43xx_evm_usomiq_defconfig	1970-01-01 03:00:00.000000000 +0300
+++ b/configs/am43xx_evm_usomiq_defconfig	2019-05-24 15:48:21.412948048 +0300
@@ -0,0 +1,65 @@
+CONFIG_ARM=y
+CONFIG_ARCH_OMAP2PLUS=y
+CONFIG_TI_COMMON_CMD_OPTIONS=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_AM43XX=y
+CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm"
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1"
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL=y
+CONFIG_SPL_ETH_SUPPORT=y
+CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_NET_SUPPORT=y
+CONFIG_SPL_NET_VCI_STRING="AM43xx U-Boot SPL"
+CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_USB_GADGET_SUPPORT=y
+CONFIG_SPL_USBETH_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SPL=y
+CONFIG_CMD_SPL_NAND_OFS=0x00100000
+CONFIG_CMD_SPL_WRITE_SIZE=0x40000
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_NAND=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDIDS_DEFAULT="nand0=nand.0"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:256k(NAND.SPL),256k(NAND.SPL.backup1),256k(NAND.SPL.backup2),256k(NAND.SPL.backup3),512k(NAND.u-boot-spl-os),1m(NAND.u-boot),256k(NAND.u-boot-env),256k(NAND.u-boot-env.backup1),7m(NAND.kernel),-(NAND.file-system)"
+CONFIG_ISO_PARTITION=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_LIST="am437x-gp-evm am437x-sk-evm am43x-epos-evm am437x-idk-evm am437x-usomiq"
+CONFIG_DM=y
+# CONFIG_BLK is not set
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_OMAP_HS=y
+CONFIG_NAND=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_PHYLIB=y
+# CONFIG_DM_ETH is not set
+CONFIG_NETDEVICES=y
+CONFIG_PHY_SMSC=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
+CONFIG_TI_QSPI=y
+CONFIG_TIMER=y
+CONFIG_OMAP_TIMER=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_OMAP=y
+CONFIG_USB_DWC3_PHY_OMAP=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0403
+CONFIG_USB_GADGET_PRODUCT_NUM=0xbd00
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_ETHER=y
diff -urbN a/configs/am43xx_evm_usomiq_nand4k_defconfig b/configs/am43xx_evm_usomiq_nand4k_defconfig
--- a/configs/am43xx_evm_usomiq_nand4k_defconfig	1970-01-01 03:00:00.000000000 +0300
+++ b/configs/am43xx_evm_usomiq_nand4k_defconfig	2019-05-24 15:48:39.388413879 +0300
@@ -0,0 +1,65 @@
+CONFIG_ARM=y
+CONFIG_ARCH_OMAP2PLUS=y
+CONFIG_TI_COMMON_CMD_OPTIONS=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_AM43XX=y
+CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm"
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1,NAND_4K"
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL=y
+CONFIG_SPL_ETH_SUPPORT=y
+CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_NET_SUPPORT=y
+CONFIG_SPL_NET_VCI_STRING="AM43xx U-Boot SPL"
+CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_USB_GADGET_SUPPORT=y
+CONFIG_SPL_USBETH_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SPL=y
+CONFIG_CMD_SPL_NAND_OFS=0x00100000
+CONFIG_CMD_SPL_WRITE_SIZE=0x40000
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_NAND=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDIDS_DEFAULT="nand0=nand.0"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:256k(NAND.SPL),256k(NAND.SPL.backup1),256k(NAND.SPL.backup2),256k(NAND.SPL.backup3),512k(NAND.u-boot-spl-os),1m(NAND.u-boot),256k(NAND.u-boot-env),256k(NAND.u-boot-env.backup1),7m(NAND.kernel),-(NAND.file-system)"
+CONFIG_ISO_PARTITION=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_LIST="am437x-gp-evm am437x-sk-evm am43x-epos-evm am437x-idk-evm am437x-usomiq"
+CONFIG_DM=y
+# CONFIG_BLK is not set
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_OMAP_HS=y
+CONFIG_NAND=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_PHYLIB=y
+# CONFIG_DM_ETH is not set
+CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
+CONFIG_TI_QSPI=y
+CONFIG_TIMER=y
+CONFIG_OMAP_TIMER=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_OMAP=y
+CONFIG_USB_DWC3_PHY_OMAP=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0403
+CONFIG_USB_GADGET_PRODUCT_NUM=0xbd00
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_ETHER=y
diff -urbN a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
--- a/include/configs/am43xx_evm.h	2018-12-16 09:28:22.000000000 +0300
+++ b/include/configs/am43xx_evm.h	2019-03-29 17:55:51.374272491 +0300
@@ -121,15 +121,91 @@
 #define CONFIG_ENV_SECT_SIZE           (64 << 10) /* 64 KB sectors */
 #define CONFIG_ENV_OFFSET              0x110000
 #define CONFIG_ENV_OFFSET_REDUND       0x120000
+#elif defined(CONFIG_EMMC_BOOT)
+#define CONFIG_SYS_MMC_ENV_DEV		1
+#define CONFIG_SYS_MMC_ENV_PART		2
+#define CONFIG_ENV_OFFSET		0x0
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_SYS_MMC_MAX_DEVICE	2
+#elif defined(CONFIG_ENV_IS_IN_NAND)
 #endif
 
 /* SPI */
 #define CONFIG_TI_SPI_MMAP
-#define CONFIG_QSPI_SEL_GPIO                   48
+#define CONFIG_QSPI_SEL_GPIO                   153
 #define CONFIG_SF_DEFAULT_SPEED                48000000
 #define CONFIG_SF_DEFAULT_MODE                 SPI_MODE_3
 #define CONFIG_QSPI_QUAD_SUPPORT
 #define CONFIG_TI_EDMA3
+#define CONFIG_SPI_FLASH_STMICRO
+
+#define EEPROM_PROGRAMMING \
+        "eeprom_dump=i2c dev 0; " \
+                "i2c md 0x50 0x00.2 20; " \
+                "\0" \
+        "eeprom_blank=i2c dev 0; " \
+                "i2c mw 0x50 0x00.2 ff; " \
+                "i2c mw 0x50 0x01.2 ff; " \
+                "i2c mw 0x50 0x02.2 ff; " \
+                "i2c mw 0x50 0x03.2 ff; " \
+                "i2c mw 0x50 0x04.2 ff; " \
+                "i2c mw 0x50 0x05.2 ff; " \
+                "i2c mw 0x50 0x06.2 ff; " \
+                "i2c mw 0x50 0x07.2 ff; " \
+                "i2c mw 0x50 0x08.2 ff; " \
+                "i2c mw 0x50 0x09.2 ff; " \
+                "i2c mw 0x50 0x0a.2 ff; " \
+                "i2c mw 0x50 0x0b.2 ff; " \
+                "i2c mw 0x50 0x0c.2 ff; " \
+                "i2c mw 0x50 0x0d.2 ff; " \
+                "i2c mw 0x50 0x0e.2 ff; " \
+                "i2c mw 0x50 0x0f.2 ff; " \
+                "i2c mw 0x50 0x10.2 ff; " \
+                "i2c mw 0x50 0x11.2 ff; " \
+                "i2c mw 0x50 0x12.2 ff; " \
+                "i2c mw 0x50 0x13.2 ff; " \
+                "i2c mw 0x50 0x14.2 ff; " \
+                "i2c mw 0x50 0x15.2 ff; " \
+                "i2c mw 0x50 0x16.2 ff; " \
+                "i2c mw 0x50 0x17.2 ff; " \
+                "i2c mw 0x50 0x18.2 ff; " \
+                "i2c mw 0x50 0x19.2 ff; " \
+                "i2c mw 0x50 0x1a.2 ff; " \
+                "i2c mw 0x50 0x1b.2 ff; " \
+                "i2c mw 0x50 0x1c.2 ff; " \
+                "i2c mw 0x50 0x1d.2 ff; " \
+                "i2c mw 0x50 0x1e.2 ff; " \
+                "i2c mw 0x50 0x1f.2 ff; " \
+                "\0" \
+        "eeprom_usomiq= " \
+                "i2c mw 0x50 0x00.2 aa; " \
+                "i2c mw 0x50 0x01.2 55; " \
+                "i2c mw 0x50 0x02.2 33; " \
+                "i2c mw 0x50 0x03.2 ee; " \
+                "i2c mw 0x50 0x04.2 41; " \
+                "i2c mw 0x50 0x05.2 4d; " \
+                "i2c mw 0x50 0x06.2 34; " \
+                "i2c mw 0x50 0x07.2 33; " \
+                "i2c mw 0x50 0x08.2 55; " \
+                "i2c mw 0x50 0x09.2 53; " \
+                "i2c mw 0x50 0x0a.2 4f; " \
+                "i2c mw 0x50 0x0b.2 4d; " \
+                "\0" \
+        "eeprom_spider= " \
+                "i2c mw 0x50 0x00.2 aa; " \
+                "i2c mw 0x50 0x01.2 55; " \
+                "i2c mw 0x50 0x02.2 33; " \
+                "i2c mw 0x50 0x03.2 ee; " \
+                "i2c mw 0x50 0x04.2 41; " \
+                "i2c mw 0x50 0x05.2 4d; " \
+                "i2c mw 0x50 0x06.2 34; " \
+                "i2c mw 0x50 0x07.2 33; " \
+                "i2c mw 0x50 0x08.2 53; " \
+                "i2c mw 0x50 0x09.2 50; " \
+                "i2c mw 0x50 0x0a.2 44; " \
+                "i2c mw 0x50 0x0b.2 52; " \
+                "\0" \
 
 #ifndef CONFIG_SPL_BUILD
 #include <environment/ti/dfu.h>
@@ -195,11 +271,16 @@
 			"setenv fdtfile am437x-sk-evm.dtb; fi; " \
 		"if test $board_name = AM43_IDK; then " \
 			"setenv fdtfile am437x-idk-evm.dtb; fi; " \
+		"if test $board_name = AM43USOM; then " \
+			"setenv fdtfile am437x-usomiq.dtb; fi; " \
+		"if test $board_name = AM43SPDR; then " \
+			"setenv fdtfile am437x-spider.dtb; fi; " \
 		"if test $fdtfile = undefined; then " \
 			"echo WARNING: Could not determine device tree; fi; \0" \
 	NANDARGS \
 	NETARGS \
 	DFUARGS \
+        EEPROM_PROGRAMMING \
 
 #define CONFIG_BOOTCOMMAND \
 	"if test ${boot_fit} -eq 1; then "	\
@@ -233,12 +314,10 @@
 /* NAND support */
 #ifdef CONFIG_NAND
 /* NAND: device related configs */
+#ifdef CONFIG_NAND_4K
 #define CONFIG_SYS_NAND_PAGE_SIZE	4096
 #define CONFIG_SYS_NAND_OOBSIZE		224
 #define CONFIG_SYS_NAND_BLOCK_SIZE	(256*1024)
-#define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
-					 CONFIG_SYS_NAND_PAGE_SIZE)
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
 /* NAND: driver related configs */
 #define CONFIG_SYS_NAND_ONFI_DETECTION
 #define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH16_CODE_HW
@@ -267,12 +346,6 @@
 			}
 #define CONFIG_SYS_NAND_ECCSIZE		512
 #define CONFIG_SYS_NAND_ECCBYTES	26
-#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x00180000
-/* NAND: SPL related configs */
-/* NAND: SPL falcon mode configs */
-#ifdef CONFIG_SPL_OS_BOOT
-#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS	0x00300000 /* kernel offset */
-#endif
 #define NANDARGS \
 	"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
 	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
@@ -287,6 +360,47 @@
 		"nand read ${fdtaddr} NAND.u-boot-spl-os; " \
 		"nand read ${loadaddr} NAND.kernel; " \
 		"bootz ${loadaddr} - ${fdtaddr}\0"
+#else
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
+/* NAND: driver related configs */
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH8_CODE_HW
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
+					 10, 11, 12, 13, 14, 15, 16, 17, \
+					 18, 19, 20, 21, 22, 23, 24, 25, \
+					 26, 27, 28, 29, 30, 31, 32, 33, \
+					 34, 35, 36, 37, 38, 39, 40, 41, \
+					 42, 43, 44, 45, 46, 47, 48, 49, \
+					 50, 51, 52, 53, 54, 55, 56, 57, }
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	14
+#define NANDARGS \
+	"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
+	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
+	"nandargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=${nandroot} " \
+		"rootfstype=${nandrootfstype}\0" \
+	"nandroot=ubi0:rootfs rw ubi.mtd=NAND.file-system,2048\0" \
+	"nandrootfstype=ubifs rootwait=1\0" \
+	"nandboot=echo Booting from nand ...; " \
+		"run nandargs; " \
+		"nand read ${fdtaddr} NAND.u-boot-spl-os; " \
+		"nand read ${loadaddr} NAND.kernel; " \
+		"bootz ${loadaddr} - ${fdtaddr}\0"
+#endif
+#define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
+					 CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x00180000
+/* NAND: SPL related configs */
+/* NAND: SPL falcon mode configs */
+#ifdef CONFIG_SPL_OS_BOOT
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS	0x00300000 /* kernel offset */
+#endif
 #define NANDBOOT			"run nandboot; "
 #else /* !CONFIG_NAND */
 #define NANDARGS
