diff --git a/patch.sh b/patch.sh
index bf0c7fc..f70d606 100644
--- a/patch.sh
+++ b/patch.sh
@@ -636,6 +636,11 @@ sgx () {
 	${git} "${DIR}/patches/sgx/0006-arm-Export-cache-flush-management-symbols-when-MULTI.patch"
 }
 
+usomiq () {
+	git apply "${DIR}/patches/usomiq/0001-add-usomiq-dts.patch"
+	#git apply "${DIR}/patches/usomiq/0002-add-usomiq-nand4k.patch"
+}
+
 ###
 
 #imx_next
@@ -646,6 +651,7 @@ fixes
 beaglebone
 
 sgx
+usomiq
 
 packaging_setup () {
 	cp -v "${DIR}/3rdparty/packaging/builddeb" "${DIR}/KERNEL/scripts/package"
diff --git a/patches/defconfig b/patches/defconfig
index 26b7ef3..0e603a8 100644
--- a/patches/defconfig
+++ b/patches/defconfig
@@ -1,6 +1,6 @@
 #
 # Automatically generated file; DO NOT EDIT.
-# Linux/arm 3.18.1 Kernel Configuration
+# Linux/arm 3.18.5 Kernel Configuration
 #
 CONFIG_ARM=y
 CONFIG_ARM_HAS_SG_CHAIN=y
@@ -1520,14 +1520,13 @@ CONFIG_MTD_SST25L=m
 CONFIG_MTD_NAND_ECC=y
 # CONFIG_MTD_NAND_ECC_SMC is not set
 CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_BCH=y
-CONFIG_MTD_NAND_ECC_BCH=y
+# CONFIG_MTD_NAND_ECC_BCH is not set
 # CONFIG_MTD_SM_COMMON is not set
 # CONFIG_MTD_NAND_DENALI is not set
 # CONFIG_MTD_NAND_GPIO is not set
-CONFIG_MTD_NAND_OMAP2=m
-# CONFIG_MTD_NAND_OMAP_BCH is not set
-# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set
+CONFIG_MTD_NAND_OMAP2=y
+CONFIG_MTD_NAND_OMAP_BCH=y
+CONFIG_MTD_NAND_OMAP_BCH_BUILD=y
 CONFIG_MTD_NAND_IDS=y
 # CONFIG_MTD_NAND_DISKONCHIP is not set
 # CONFIG_MTD_NAND_DOCG4 is not set
@@ -1548,7 +1547,7 @@ CONFIG_MTD_QINFO_PROBE=m
 CONFIG_MTD_LPDDR2_NVM=m
 CONFIG_MTD_SPI_NOR=m
 CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
-CONFIG_MTD_UBI=m
+CONFIG_MTD_UBI=y
 CONFIG_MTD_UBI_WL_THRESHOLD=4096
 CONFIG_MTD_UBI_BEB_LIMIT=20
 # CONFIG_MTD_UBI_FASTMAP is not set
@@ -5062,7 +5061,7 @@ CONFIG_JFFS2_RTIME=y
 CONFIG_JFFS2_CMODE_PRIORITY=y
 # CONFIG_JFFS2_CMODE_SIZE is not set
 # CONFIG_JFFS2_CMODE_FAVOURLZO is not set
-CONFIG_UBIFS_FS=m
+CONFIG_UBIFS_FS=y
 CONFIG_UBIFS_FS_ADVANCED_COMPR=y
 CONFIG_UBIFS_FS_LZO=y
 CONFIG_UBIFS_FS_ZLIB=y
@@ -5563,7 +5562,7 @@ CONFIG_CRYPTO_TWOFISH_COMMON=m
 #
 # Compression
 #
-CONFIG_CRYPTO_DEFLATE=m
+CONFIG_CRYPTO_DEFLATE=y
 CONFIG_CRYPTO_ZLIB=m
 CONFIG_CRYPTO_LZO=y
 CONFIG_CRYPTO_LZ4=m
diff --git a/patches/usomiq/0001-add-usomiq-dts.patch b/patches/usomiq/0001-add-usomiq-dts.patch
new file mode 100644
index 0000000..1dcab33
--- /dev/null
+++ b/patches/usomiq/0001-add-usomiq-dts.patch
@@ -0,0 +1,279 @@
+diff --git a/arch/arm/boot/dts/am335x-nand.dtsi b/arch/arm/boot/dts/am335x-nand.dtsi
+new file mode 100644
+index 0000000..a3dcc27
+--- /dev/null
++++ b/arch/arm/boot/dts/am335x-nand.dtsi
+@@ -0,0 +1,131 @@
++&ocp {
++    P9_11_pinmux {
++	status = "disabled";
++    };
++    P9_13_pinmux {
++	status = "disabled";
++    };
++    P8_26_pinmux {
++	status = "disabled";
++    };
++    P8_07_pinmux {
++	status = "disabled";
++    };
++    P8_08_pinmux {
++	status = "disabled";
++    };
++    P8_09_pinmux {
++	status = "disabled";
++    };
++    P8_10_pinmux {
++	status = "disabled";
++    };
++};
++
++&elm {
++	status = "okay";
++};
++
++&am33xx_pinmux {
++	nandflash_pins_s0: nandflash_pins_s0 {
++		pinctrl-single,pins = <
++			0x0 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad0.gpmc_ad0 */
++			0x4 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad1.gpmc_ad1 */
++			0x8 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad2.gpmc_ad2 */
++			0xc (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad3.gpmc_ad3 */
++			0x10 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad4.gpmc_ad4 */
++			0x14 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad5.gpmc_ad5 */
++			0x18 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad6.gpmc_ad6 */
++			0x1c (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad7.gpmc_ad7 */
++			0x70 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_wait0.gpmc_wait0 */
++			0x74 (PIN_INPUT_PULLUP | MUX_MODE7)	/* gpmc_wpn.gpio0_30 */
++			0x7c (PIN_OUTPUT | MUX_MODE0)		/* gpmc_csn0.gpmc_csn0  */
++			0x90 (PIN_OUTPUT | MUX_MODE0)		/* gpmc_advn_ale.gpmc_advn_ale */
++			0x94 (PIN_OUTPUT | MUX_MODE0)		/* gpmc_oen_ren.gpmc_oen_ren */
++			0x98 (PIN_OUTPUT | MUX_MODE0)		/* gpmc_wen.gpmc_wen */
++			0x9c (PIN_OUTPUT | MUX_MODE0)		/* gpmc_be0n_cle.gpmc_be0n_cle */
++		>;
++	};
++};
++
++&gpmc {
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&nandflash_pins_s0>;
++	ranges = <0 0 0x08000000 0x40000000>;	/* CS0: NAND */
++	nand@0,0 {
++		reg = <0 0 0>; /* CS0, offset 0 */
++		ti,nand-ecc-opt = "bch8";
++		ti,elm-id = <&elm>;
++		nand-bus-width = <8>;
++		gpmc,device-width = <1>;
++		gpmc,sync-clk-ps = <0>;
++		gpmc,cs-on-ns = <0>;
++		gpmc,cs-rd-off-ns = <44>;
++		gpmc,cs-wr-off-ns = <44>;
++		gpmc,adv-on-ns = <6>;
++		gpmc,adv-rd-off-ns = <34>;
++		gpmc,adv-wr-off-ns = <44>;
++		gpmc,we-on-ns = <0>;
++		gpmc,we-off-ns = <40>;
++		gpmc,oe-on-ns = <0>;
++		gpmc,oe-off-ns = <54>;
++		gpmc,access-ns = <64>;
++		gpmc,rd-cycle-ns = <82>;
++		gpmc,wr-cycle-ns = <82>;
++		gpmc,wait-on-read = "true";
++		gpmc,wait-on-write = "true";
++		gpmc,bus-turnaround-ns = <0>;
++		gpmc,cycle2cycle-delay-ns = <0>;
++		gpmc,clk-activation-ns = <0>;
++		gpmc,wait-monitoring-ns = <0>;
++		gpmc,wr-access-ns = <40>;
++		gpmc,wr-data-mux-bus-ns = <0>;
++		/* MTD partition table */
++		/* All SPL-* partitions are sized to minimal length
++		 * which can be independently programmable. For
++		 * NAND flash this is equal to size of erase-block */
++		#address-cells = <1>;
++		#size-cells = <1>;
++		partition@0 {
++			label = "NAND.SPL";
++			reg = <0x00000000 0x000020000>;
++		};
++		partition@1 {
++			label = "NAND.SPL.backup1";
++			reg = <0x00020000 0x00020000>;
++		};
++		partition@2 {
++			label = "NAND.SPL.backup2";
++			reg = <0x00040000 0x00020000>;
++		};
++		partition@3 {
++			label = "NAND.SPL.backup3";
++			reg = <0x00060000 0x00020000>;
++		};
++		partition@4 {
++			label = "NAND.u-boot-spl-os";
++			reg = <0x00080000 0x00040000>;
++		};
++		partition@5 {
++			label = "NAND.u-boot";
++			reg = <0x000C0000 0x00100000>;
++		};
++		partition@6 {
++			label = "NAND.u-boot-env";
++			reg = <0x001C0000 0x00020000>;
++		};
++		partition@7 {
++			label = "NAND.u-boot-env.backup1";
++			reg = <0x001E0000 0x00020000>;
++		};
++		partition@8 {
++			label = "NAND.kernel";
++			reg = <0x00200000 0x00800000>;
++		};
++		partition@9 {
++			label = "NAND.file-system";
++			reg = <0x00A00000 0x40000000>;
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/am335x-usomiq.dts b/arch/arm/boot/dts/am335x-usomiq.dts
+new file mode 100644
+index 0000000..7efc8b7
+--- /dev/null
++++ b/arch/arm/boot/dts/am335x-usomiq.dts
+@@ -0,0 +1,122 @@
++/*
++ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++/dts-v1/;
++
++#include "am33xx.dtsi"
++#include "am335x-bone-common.dtsi"
++#include "am335x-bone-common-pinmux.dtsi"
++
++/ {
++	model = "TI AM335x uSomIQ";
++	compatible = "ti,am335x-usomiq", "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx";
++};
++
++&ldo3_reg {
++	regulator-min-microvolt = <1800000>;
++	regulator-max-microvolt = <1800000>;
++	regulator-always-on;
++};
++
++&mmc1 {
++	vmmc-supply = <&vmmcsd_fixed>;
++};
++/*
++&am33xx_pinmux {
++	pinctrl-names = "default";
++	pinctrl-0 = <&clkout2_pin>;
++};*/
++
++&rtc {
++	ti,system-power-controller;
++};
++
++#include "am335x-nand.dtsi"
++/* Max Core Speed */
++#include "am335x-boneblack-1ghz.dtsi"
++/* #include "am335x-boneblack-800mhz.dtsi" */
++
++/* spi0: */
++/* P9.17 spi0_cs0 */
++/* P9.18 spi0_d1 */
++/* P9.21 spi0_d0 */
++/* P9.22 spi0_sclk */
++/* #include "am335x-bone-spi0-spidev.dtsi" */
++
++/* spi1: */
++/* P9.31 spi1_sclk */
++/* P9.29 spi1_d0 */
++/* P9.30 spi1_d1 */
++/* P9.28 spi1_cs0 */
++/* #include "am335x-bone-spi1-spidev.dtsi" */
++
++/* spi1a: */
++/* P9.42 spi1_sclk */
++/* P9.29 spi1_d0 */
++/* P9.30 spi1_d1 */
++/* P9.20 spi1_cs0 */
++/* #include "am335x-bone-spi1a-spidev.dtsi" */
++
++/* uart1: P9.24, P9.26 */
++#include "am335x-ttyO1.dtsi"
++/* #include "am335x-bone-ttyO1.dtsi" */
++/* uart2: P9.21, P9.22 */
++#include "am335x-ttyO2.dtsi"
++/* #include "am335x-bone-ttyO2.dtsi" */
++/* uart4: P9.11, P9.13 */
++/* #include "am335x-ttyO4.dtsi" */
++/* #include "am335x-bone-ttyO4.dtsi" */
++/* uart5: P8.37, P8.38 boneblack: hdmi has to be disabled for ttyO5 */
++/* #include "am335x-ttyO5.dtsi" */
++/* #include "am335x-bone-ttyO5.dtsi" */
++
++/* Capes */
++/* http://elinux.org/4D_4.3_LCD_CAPE */
++/* 4DCAPE-43 (Non Touch version): */
++/* #include "am335x-bone-4dcape-43.dtsi" */
++/* 4DCAPE-43T (Resistive Touch version): */
++/* #include "am335x-bone-4dcape-43t.dtsi" */
++
++/* http://www.4dsystems.com.au/product/4DCAPE_70T/ */
++/* 4DCAPE-70 (Non Touch version): */
++/* #include "am335x-bone-4dcape-70.dtsi" */
++/* 4DCAPE-70T (Resistive Touch version): */
++/* #include "am335x-bone-4dcape-70t.dtsi" */
++
++/* http://elinux.org/CircuitCo:Audio_Cape_RevA */
++/* #include "am335x-bone-audio-reva.dtsi" */
++
++/* http://elinux.org/CircuitCo:Audio_Cape_RevB */
++/* Pins: P9.24, P9.28, P9.29, P9.31, P9.30 */
++/* #include "am335x-bone-audio-revb.dtsi" */
++
++/* http://elinux.org/CircuitCo:BeagleBone_LCD3 */
++/* #include "am335x-bone-lcd3-01-00a2.dtsi" */
++
++/* http://elinux.org/CircuitCo:BeagleBone_LCD4 */
++/* #include "am335x-bone-lcd4-01-00a1.dtsi" */
++
++/* http://elinux.org/CircuitCo:BeagleBone_LCD7 */
++/* am335x-boneblack: emmc has to be disabled for lcd7-01-00a2 */
++/* #include "am335x-bone-lcd7-01-00a2.dtsi" */
++/* #include "am335x-bone-lcd7-01-00a3.dtsi" */
++
++/* http://www.chipsee.com/product/evm/beagle/beaglebone-black-expansion-capacitive.html */
++/* #include "am335x-bone-bbb-exp-c.dtsi" */
++
++/* http://elinux.org/CircuitCo:RTC_Cape */
++/* i2c1: P9.17, P9.18 */
++/* gpio: P8.26 (mfp: wakeup) */
++/* #include "am335x-bone-rtc-01-00a1.dtsi" */
++
++/* http://elinux.org/Cryptotronix:CryptoCape */
++/* uart4: P9.11, P9.13 */
++/* gpio: gpio1 13 gpio1 17 (gpio NOT IMPLEMENTED YET) */
++/* #include "am335x-bone-crypto-00a0.dtsi" */
++
++/* http://elinux.org/CircuitCo:Basic_Proto_Cape */
++/* #include "am335x-bone-basic-proto-cape.dtsi" */
+diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
+index bcbcba1..8cb39ce 100644
+--- a/arch/arm/boot/dts/Makefile
++++ b/arch/arm/boot/dts/Makefile
+@@ -369,7 +369,8 @@ dtb-$(CONFIG_SOC_AM33XX) += am335x-base0033.dtb \
+ 	am335x-evm.dtb \
+ 	am335x-evmsk.dtb \
+ 	am335x-nano.dtb \
+-	am335x-pepper.dtb
++	am335x-pepper.dtb \
++	am335x-usomiq.dtb
+ dtb-$(CONFIG_ARCH_OMAP4) += omap4-duovero-parlor.dtb \
+ 	omap4-panda.dtb \
+ 	omap4-panda-a4.dtb \
diff --git a/patches/usomiq/0002-add-usomiq-nand4k.patch b/patches/usomiq/0002-add-usomiq-nand4k.patch
new file mode 100644
index 0000000..6b271e8
--- /dev/null
+++ b/patches/usomiq/0002-add-usomiq-nand4k.patch
@@ -0,0 +1,152 @@
+diff --git a/arch/arm/boot/dts/am335x-usomiq.dts b/arch/arm/boot/dts/am335x-usomiq.dts
+index 7efc8b7..1ffafe4 100644
+--- a/arch/arm/boot/dts/am335x-usomiq.dts
++++ b/arch/arm/boot/dts/am335x-usomiq.dts
+@@ -35,7 +35,10 @@
+ 	ti,system-power-controller;
+ };
+ 
++/* NAND support */
+ #include "am335x-nand.dtsi"
++/*#include "am335x-nand4k.dtsi"*/
++
+ /* Max Core Speed */
+ #include "am335x-boneblack-1ghz.dtsi"
+ /* #include "am335x-boneblack-800mhz.dtsi" */
+diff --git a/arch/arm/boot/dts/am335x-nand4k.dtsi b/arch/arm/boot/dts/am335x-nand4k.dtsi
+new file mode 100644
+index 0000000..63cef88
+--- /dev/null
++++ b/arch/arm/boot/dts/am335x-nand4k.dtsi
+@@ -0,0 +1,131 @@
++&ocp {
++    P9_11_pinmux {
++	status = "disabled";
++    };
++    P9_13_pinmux {
++	status = "disabled";
++    };
++    P8_26_pinmux {
++	status = "disabled";
++    };
++    P8_07_pinmux {
++	status = "disabled";
++    };
++    P8_08_pinmux {
++	status = "disabled";
++    };
++    P8_09_pinmux {
++	status = "disabled";
++    };
++    P8_10_pinmux {
++	status = "disabled";
++    };
++};
++
++&elm {
++	status = "okay";
++};
++
++&am33xx_pinmux {
++	nandflash_pins_s0: nandflash_pins_s0 {
++		pinctrl-single,pins = <
++			0x0 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad0.gpmc_ad0 */
++			0x4 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad1.gpmc_ad1 */
++			0x8 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad2.gpmc_ad2 */
++			0xc (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad3.gpmc_ad3 */
++			0x10 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad4.gpmc_ad4 */
++			0x14 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad5.gpmc_ad5 */
++			0x18 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad6.gpmc_ad6 */
++			0x1c (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad7.gpmc_ad7 */
++			0x70 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_wait0.gpmc_wait0 */
++			0x74 (PIN_INPUT_PULLUP | MUX_MODE7)	/* gpmc_wpn.gpio0_30 */
++			0x7c (PIN_OUTPUT | MUX_MODE0)		/* gpmc_csn0.gpmc_csn0  */
++			0x90 (PIN_OUTPUT | MUX_MODE0)		/* gpmc_advn_ale.gpmc_advn_ale */
++			0x94 (PIN_OUTPUT | MUX_MODE0)		/* gpmc_oen_ren.gpmc_oen_ren */
++			0x98 (PIN_OUTPUT | MUX_MODE0)		/* gpmc_wen.gpmc_wen */
++			0x9c (PIN_OUTPUT | MUX_MODE0)		/* gpmc_be0n_cle.gpmc_be0n_cle */
++		>;
++	};
++};
++
++&gpmc {
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&nandflash_pins_s0>;
++	ranges = <0 0 0x08000000 0x40000000>;	/* CS0: NAND */
++	nand@0,0 {
++		reg = <0 0 0>; /* CS0, offset 0 */
++		ti,nand-ecc-opt = "bch16";
++		ti,elm-id = <&elm>;
++		nand-bus-width = <8>;
++		gpmc,device-width = <1>;
++		gpmc,sync-clk-ps = <0>;
++		gpmc,cs-on-ns = <0>;
++		gpmc,cs-rd-off-ns = <44>;
++		gpmc,cs-wr-off-ns = <44>;
++		gpmc,adv-on-ns = <6>;
++		gpmc,adv-rd-off-ns = <34>;
++		gpmc,adv-wr-off-ns = <44>;
++		gpmc,we-on-ns = <0>;
++		gpmc,we-off-ns = <40>;
++		gpmc,oe-on-ns = <0>;
++		gpmc,oe-off-ns = <54>;
++		gpmc,access-ns = <64>;
++		gpmc,rd-cycle-ns = <82>;
++		gpmc,wr-cycle-ns = <82>;
++		gpmc,wait-on-read = "true";
++		gpmc,wait-on-write = "true";
++		gpmc,bus-turnaround-ns = <0>;
++		gpmc,cycle2cycle-delay-ns = <0>;
++		gpmc,clk-activation-ns = <0>;
++		gpmc,wait-monitoring-ns = <0>;
++		gpmc,wr-access-ns = <40>;
++		gpmc,wr-data-mux-bus-ns = <0>;
++		/* MTD partition table */
++		/* All SPL-* partitions are sized to minimal length
++		 * which can be independently programmable. For
++		 * NAND flash this is equal to size of erase-block */
++		#address-cells = <1>;
++		#size-cells = <1>;
++		partition@0 {
++			label = "NAND.SPL";
++			reg = <0x00000000 0x00040000>;
++		};
++		partition@1 {
++			label = "NAND.SPL.backup1";
++			reg = <0x00040000 0x00040000>;
++		};
++		partition@2 {
++			label = "NAND.SPL.backup2";
++			reg = <0x00080000 0x00040000>;
++		};
++		partition@3 {
++			label = "NAND.SPL.backup3";
++			reg = <0x000c0000 0x00040000>;
++		};
++		partition@4 {
++			label = "NAND.u-boot-spl-os";
++			reg = <0x00100000 0x00080000>;
++		};
++		partition@5 {
++			label = "NAND.u-boot";
++			reg = <0x00180000 0x00100000>;
++		};
++		partition@6 {
++			label = "NAND.u-boot-env";
++			reg = <0x00280000 0x00040000>;
++		};
++		partition@7 {
++			label = "NAND.u-boot-env.backup1";
++			reg = <0x002c0000 0x00040000>;
++		};
++		partition@8 {
++			label = "NAND.kernel";
++			reg = <0x00300000 0x00700000>;
++		};
++		partition@9 {
++			label = "NAND.file-system";
++			reg = <0x00a00000 0x40000000>;
++		};
++	};
++};
