diff --git a/patch.sh b/patch.sh
index cde9c2d..957c7ed 100644
--- a/patch.sh
+++ b/patch.sh
@@ -933,6 +933,11 @@ am33x_after () {
 	#cp -v ../am33x-cm3/bin/am335x-pm-firmware.bin ./firmware/
 	#git add -f ./firmware/am335x-pm-firmware.bin
 	${git} "${DIR}/patches/firmware/0001-firmware-add-for-beaglebone.patch"
+
+	echo "uSomIQ patches"
+	git apply "${DIR}/patches/usomiq/add-usomiq-dts.patch"
+	git apply "${DIR}/patches/usomiq/0001-fix-nand-map-comply-3.18.patch"
+	git apply "${DIR}/patches/usomiq/0002-fix-dvi-capes.patch"
 }
 
 saucy () {
diff --git a/patches/defconfig b/patches/defconfig
index ab6fb34..5dbcdda 100644
--- a/patches/defconfig
+++ b/patches/defconfig
@@ -1398,6 +1398,8 @@ CONFIG_MTD_CFI_UTIL=y
 # CONFIG_MTD_DOC2001 is not set
 # CONFIG_MTD_DOC2001PLUS is not set
 # CONFIG_MTD_DOCG3 is not set
+CONFIG_BCH_CONST_M=13
+CONFIG_BCH_CONST_T=8
 CONFIG_MTD_NAND_ECC=y
 # CONFIG_MTD_NAND_ECC_SMC is not set
 CONFIG_MTD_NAND=y
@@ -1407,7 +1409,9 @@ CONFIG_MTD_NAND=y
 # CONFIG_MTD_NAND_DENALI is not set
 # CONFIG_MTD_NAND_GPIO is not set
 CONFIG_MTD_NAND_OMAP2=y
-# CONFIG_MTD_NAND_OMAP_BCH is not set
+CONFIG_MTD_NAND_OMAP_BCH=y
+CONFIG_MTD_NAND_OMAP_BCH8=y
+# CONFIG_MTD_NAND_OMAP_BCH4 is not set
 CONFIG_MTD_NAND_IDS=y
 # CONFIG_MTD_NAND_DISKONCHIP is not set
 # CONFIG_MTD_NAND_DOCG4 is not set
@@ -4206,7 +4210,10 @@ CONFIG_JFFS2_RUBIN=y
 CONFIG_JFFS2_CMODE_PRIORITY=y
 # CONFIG_JFFS2_CMODE_SIZE is not set
 # CONFIG_JFFS2_CMODE_FAVOURLZO is not set
-# CONFIG_UBIFS_FS is not set
+CONFIG_UBIFS_FS=y
+# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
+CONFIG_UBIFS_FS_LZO=y
+CONFIG_UBIFS_FS_ZLIB=y
 CONFIG_LOGFS=m
 CONFIG_CRAMFS=m
 CONFIG_SQUASHFS=m
@@ -4650,6 +4657,8 @@ CONFIG_DECOMPRESS_LZMA=y
 CONFIG_DECOMPRESS_XZ=y
 CONFIG_DECOMPRESS_LZO=y
 CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_BCH=y
+CONFIG_BCH_CONST_PARAMS=y
 CONFIG_TEXTSEARCH=y
 CONFIG_TEXTSEARCH_KMP=m
 CONFIG_TEXTSEARCH_BM=m
diff --git a/patches/usomiq/0001-fix-nand-map-comply-3.18.patch b/patches/usomiq/0001-fix-nand-map-comply-3.18.patch
new file mode 100644
index 0000000..e866e1a
--- /dev/null
+++ b/patches/usomiq/0001-fix-nand-map-comply-3.18.patch
@@ -0,0 +1,55 @@
+diff --git a/arch/arm/boot/dts/am335x-usomiq.dts b/arch/arm/boot/dts/am335x-usomiq.dts
+index a6ffd81..bd20062 100644
+--- a/arch/arm/boot/dts/am335x-usomiq.dts
++++ b/arch/arm/boot/dts/am335x-usomiq.dts
+@@ -555,7 +555,7 @@
+ 	status = "okay";
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&nandflash_pins_s0>;
+-	ranges = <0 0 0x08000000 0x10000000>;   /* CS0: NAND */
++	ranges = <0 0 0x08000000 0x40000000>;   /* CS0: NAND */
+ 	nand@0,0 {
+ 		reg = <0 0 0>; /* CS0, offset 0 */
+ 		nand-bus-width = <8>;
+@@ -611,28 +611,33 @@
+ 		};
+ 
+ 		partition@4 {
+-			label = "u-boot";
+-			reg = <0x00080000 0x00080000>;
++			label = "u-boot-spl-os";
++			reg = <0x00080000 0x00040000>;
+ 		};
+ 
+ 		partition@5 {
+-			label = "u-boot-spl-os";
+-			reg = <0x00100000 0x00020000>;
++			label = "u-boot";
++			reg = <0x000C0000 0x00100000>;
+ 		};
+ 
+ 		partition@6 {
+ 			label = "u-boot-env";
+-			reg = <0x00120000 0x00020000>;
++			reg = <0x001C0000 0x00020000>;
+ 		};
+ 
+ 		partition@7 {
+-			label = "kernel";
+-			reg = <0x00280000 0x00500000>;
++			label = "u-boot-env.backup1";
++			reg = <0x001E0000 0x00020000>;
+ 		};
+ 
+ 		partition@8 {
++			label = "kernel";
++			reg = <0x00200000 0x00800000>;
++		};
++
++		partition@9 {
+ 			label = "rootfs";
+-			reg = <0x00780000 0x1F880000>;
++			reg = <0x00A00000 0x40000000>;
+ 		};
+ 	};
+ };
diff --git a/patches/usomiq/0002-fix-dvi-capes.patch b/patches/usomiq/0002-fix-dvi-capes.patch
new file mode 100644
index 0000000..20b1348
--- /dev/null
+++ b/patches/usomiq/0002-fix-dvi-capes.patch
@@ -0,0 +1,60 @@
+diff --git a/firmware/capes/cape-bone-dvi-00A0.dts b/firmware/capes/cape-bone-dvi-00A0.dts
+index 577a474..453d495 100644
+--- a/firmware/capes/cape-bone-dvi-00A0.dts
++++ b/firmware/capes/cape-bone-dvi-00A0.dts
+@@ -44,7 +44,6 @@
+ 		/* the hardware IP uses */
+ 		"gpio1_18",
+ 		"gpio1_19",
+-		"gpio1_7",
+ 		"lcd";
+ 
+ 	fragment@0 {
+@@ -60,7 +59,6 @@
+ 
+ 			bone_dvi_cape_dvi_00A0_pins: pinmux_bone_dvi_cape_dvi_00A0_pins {
+ 				pinctrl-single,pins = <
+-					0x1c 0x07	/* gpmc_ad7.gpio1_7, OUTPUT | MODE7 - DVIPDn */
+ 
+ 					0xa0 0x08	/* lcd_data0.lcd_data0, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
+ 					0xa4 0x08	/* lcd_data1.lcd_data1, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
+diff --git a/firmware/capes/cape-bone-dvi-00A1.dts b/firmware/capes/cape-bone-dvi-00A1.dts
+index ac8b4c5..a7007ce 100644
+--- a/firmware/capes/cape-bone-dvi-00A1.dts
++++ b/firmware/capes/cape-bone-dvi-00A1.dts
+@@ -48,7 +48,6 @@
+ 		/* the hardware IP uses */
+ 		"gpio1_18",
+ 		"gpio1_19",
+-		"gpio1_7",
+ 		"mcasp0",
+ 		"lcd";
+ 
+@@ -65,7 +64,6 @@
+ 
+ 			bone_dvi_cape_dvi_00A1_pins: pinmux_bone_dvi_cape_dvi_00A1_pins {
+ 				pinctrl-single,pins = <
+-					0x1c 0x07	/* gpmc_ad7.gpio1_7, OUTPUT | MODE7 - DVIPDn */
+ 
+ 					0xa0 0x08	/* lcd_data0.lcd_data0, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
+ 					0xa4 0x08	/* lcd_data1.lcd_data1, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
+diff --git a/firmware/capes/cape-bone-dvi-00A2.dts b/firmware/capes/cape-bone-dvi-00A2.dts
+index 4c54804..78948fd 100644
+--- a/firmware/capes/cape-bone-dvi-00A2.dts
++++ b/firmware/capes/cape-bone-dvi-00A2.dts
+@@ -44,7 +44,6 @@
+ 		/* the hardware IP uses */
+ 		"gpio1_18",
+ 		"gpio1_19",
+-		"gpio1_7",
+ 		"lcd";
+ 
+ 	fragment@0 {
+@@ -60,7 +59,6 @@
+ 
+ 			bone_dvi_cape_dvi_00A2_pins: pinmux_bone_dvi_cape_dvi_00A2_pins {
+ 				pinctrl-single,pins = <
+-					0x1c 0x07	/* gpmc_ad7.gpio1_7, OUTPUT | MODE7 - DVIPDn */
+ 
+ 					0xa0 0x08	/* lcd_data0.lcd_data0, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
+ 					0xa4 0x08	/* lcd_data1.lcd_data1, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
diff --git a/patches/usomiq/add-usomiq-dts.patch b/patches/usomiq/add-usomiq-dts.patch
new file mode 100644
index 0000000..fdd3882
--- /dev/null
+++ b/patches/usomiq/add-usomiq-dts.patch
@@ -0,0 +1,677 @@
+diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
+index 9da016f..d3e9024 100644
+--- a/arch/arm/boot/dts/Makefile
++++ b/arch/arm/boot/dts/Makefile
+@@ -116,7 +116,8 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
+ 	am335x-bone.dtb \
+ 	am335x-boneblack.dtb \
+ 	arduino-tre.dtb \
+-	am335x-tester.dtb
++	am335x-tester.dtb \
++	am335x-usomiq.dtb
+ dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb
+ dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
+ dtb-$(CONFIG_ARCH_U8500) += snowball.dtb \
+diff --git a/drivers/misc/cape/beaglebone/capemgr.c b/drivers/misc/cape/beaglebone/capemgr.c
+index 30ed057..ddb7598 100644
+--- a/drivers/misc/cape/beaglebone/capemgr.c
++++ b/drivers/misc/cape/beaglebone/capemgr.c
+@@ -428,6 +428,13 @@ static int bone_baseboard_scan(struct bone_baseboard *bbrd)
+ 
+ 	bbrd->probed = 1;
+ 
++    /* MENTOREL: ugly hack to avoid EEPROM reading */
++    {
++        char ar[] = {0xaa, 0x55, 0x33, 0xee, 'A', '3', '3', '5', 'U', 'S', 'O', 'M', 0};
++        memcpy((char *)bbrd->signature, (char *)&ar, sizeof(ar));
++        bbrd->override = 1;
++    }
++
+ 	if (!bbrd->override) {
+ 
+ 		if (macc == NULL || macc->read == NULL) {
+diff --git a/arch/arm/boot/dts/am335x-usomiq.dts b/arch/arm/boot/dts/am335x-usomiq.dts
+new file mode 100644
+index 0000000..2dd8a6e
+--- /dev/null
++++ b/arch/arm/boot/dts/am335x-usomiq.dts
+@@ -0,0 +1,639 @@
++/*
++ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++/dts-v1/;
++
++/include/ "am33xx.dtsi"
++
++/ {
++	model = "TI AM335x uSomIQ";
++	compatible = "ti,am335x-usomiq", "ti,am33xx";
++
++	cpus {
++		cpu@0 {
++			cpu0-supply = <&dcdc2_reg>;
++		};
++	};
++
++	memory {
++		device_type = "memory";
++		reg = <0x80000000 0x10000000>; /* 256 MB */
++	};
++
++	am33xx_pinmux: pinmux@44e10800 {
++		pinctrl-names = "default";
++		pinctrl-0 = <&userled_pins>;
++
++		userled_pins: pinmux_userled_pins {
++			pinctrl-single,pins = <
++				0x54 0x7	/* gpmc_a5.gpio1_21, OUTPUT | MODE7 */
++				0x58 0x17	/* gpmc_a6.gpio1_22, OUTPUT_PULLUP | MODE7 */
++				0x5c 0x7	/* gpmc_a7.gpio1_23, OUTPUT | MODE7 */
++				0x60 0x17	/* gpmc_a8.gpio1_24, OUTPUT_PULLUP | MODE7 */
++			>;
++		};
++		i2c0_pins: pinmux_i2c0_pins {
++			pinctrl-single,pins = <
++				0x188 0x70 	/* i2c0_sda, SLEWCTRL_SLOW | INPUT_PULLUP | MODE0 */
++				0x18c 0x70	/* i2c0_scl, SLEWCTRL_SLOW | INPUT_PULLUP | MODE0 */
++			>;
++		};
++		i2c2_pins: pinmux_i2c2_pins {
++			pinctrl-single,pins = <
++				0x178 0x73 	/* uart1_ctsn.i2c2_sda, SLEWCTRL_SLOW | INPUT_PULLUP | MODE3 */
++				0x17c 0x73	/* uart1_rtsn.i2c2_scl, SLEWCTRL_SLOW | INPUT_PULLUP | MODE3 */
++			>;
++		};
++		mmc1_pins: pinmux_mmc1_pins {
++			pinctrl-single,pins = <
++				0x160 0x2f /* GPIO0_6 (PIN_INPUT | MUX_MODE7) */
++			>;
++		};
++		spi0_pins_s0: spi0_pins_s0 {
++			pinctrl-single,pins = <
++				0x150 0x30	/* spi0_sclk.spi0_sclk, INPUT_PULLUP | MODE0 */
++				0x154 0x30	/* spi0_d0.spi0_d0, INPUT_PULLUP | MODE0 */
++				0x158 0x10	/* spi0_d1.spi0_d1, OUTPUT_PULLUP | MODE0 */
++				0x15c 0x10	/* spi0_cs0.spi0_cs0, OUTPUT_PULLUP | MODE0 */
++			>;
++		};
++        nandflash_pins: nandflash_pins_s0 {
++            pinctrl-single,pins = <
++			    0x0 0x30	// (PIN_INPUT_PULLUP | MUX_MODE0)	// gpmc_ad0.gpmc_ad0
++			    0x4 0x30	// (PIN_INPUT_PULLUP | MUX_MODE0)	// gpmc_ad1.gpmc_ad1
++			    0x8 0x30	// (PIN_INPUT_PULLUP | MUX_MODE0)	// gpmc_ad2.gpmc_ad2
++			    0xc 0x30	// (PIN_INPUT_PULLUP | MUX_MODE0)	// gpmc_ad3.gpmc_ad3
++			    0x10 0x30	// (PIN_INPUT_PULLUP | MUX_MODE0)	// gpmc_ad4.gpmc_ad4
++			    0x14 0x30	//(PIN_INPUT_PULLUP | MUX_MODE0)	// gpmc_ad5.gpmc_ad5
++			    0x18 0x30	//(PIN_INPUT_PULLUP | MUX_MODE0)	// gpmc_ad6.gpmc_ad6
++			    0x1c 0x30	// (PIN_INPUT_PULLUP | MUX_MODE0)	// gpmc_ad7.gpmc_ad7
++			    0x70 0x30	// (PIN_INPUT_PULLUP | MUX_MODE0)	// gpmc_wait0.gpmc_wait0
++			    0x74 0x30	// (PIN_INPUT_PULLUP | MUX_MODE7)	// gpmc_wpn.gpio0_30
++			    0x7c 0x8	// (PIN_OUTPUT | MUX_MODE0)		// gpmc_csn0.gpmc_csn0 
++			    0x90 0x8	// (PIN_OUTPUT | MUX_MODE0)		// gpmc_advn_ale.gpmc_advn_ale
++			    0x94 0x8	// (PIN_OUTPUT | MUX_MODE0)		// gpmc_oen_ren.gpmc_oen_ren
++			    0x98 0x8	// (PIN_OUTPUT | MUX_MODE0)		// gpmc_wen.gpmc_wen
++			    0x9c 0x8	// (PIN_OUTPUT | MUX_MODE0)		// gpmc_be0n_cle.gpmc_be0n_cle
++            >;
++        };
++	};
++
++	ocp: ocp {
++
++		uart1: serial@44e09000 {
++			status = "okay";
++		};
++
++		gpio-leds {
++			compatible = "gpio-leds";
++			pinctrl-names = "default";
++			pinctrl-0 = <&userled_pins>;
++
++			led0 {
++				label = "beaglebone:green:usr0";
++				gpios = <&gpio2 21 0>;
++				linux,default-trigger = "heartbeat";
++				default-state = "off";
++			};
++
++			led1 {
++				label = "beaglebone:green:usr1";
++				gpios = <&gpio2 22 0>;
++				linux,default-trigger = "mmc0";
++				default-state = "off";
++			};
++
++			led2 {
++				label = "beaglebone:green:usr2";
++				gpios = <&gpio2 23 0>;
++				linux,default-trigger = "cpu0";
++				default-state = "off";
++			};
++
++			led3 {
++				label = "beaglebone:green:usr3";
++				gpios = <&gpio2 24 0>;
++				default-state = "off";
++				linux,default-trigger = "nand-disk";
++			};
++		};
++
++		rtc@44e3e000 {
++			ti,system-power-controller;
++		};
++	};
++
++	bone_capemgr {
++		compatible = "ti,bone-capemgr";
++		status = "okay";
++
++		eeprom = <&baseboard_eeprom>;
++
++		baseboardmaps {
++			baseboard_usomiq: board@0 {
++				board-name = "A335USOM";
++				compatible-name = "ti,beaglebone";
++			};
++		};
++
++		slots {
++			slot@0 {
++				eeprom = <&cape_eeprom0>;
++			};
++
++			slot@1 {
++				eeprom = <&cape_eeprom1>;
++			};
++
++			slot@2 {
++				eeprom = <&cape_eeprom2>;
++			};
++
++			slot@3 {
++				eeprom = <&cape_eeprom3>;
++			};
++
++			/* geiger cape version A0 without an EEPROM */
++			slot@5 {
++				ti,cape-override;
++				compatible = "kernel-command-line", "runtime";
++				board-name = "Bone-Geiger";
++				version = "00A0";
++				manufacturer = "Geiger Inc.";
++				part-number = "BB-BONE-GEIGER";
++			};
++
++			/* Nixie cape version A0 without an EEPROM */
++			slot@7 {
++				ti,cape-override;
++				compatible = "kernel-command-line", "runtime";
++				board-name = "Bone-Nixie";
++				version = "00A0";
++				manufacturer = "Ranostay Industries";
++				part-number = "BB-BONE-NIXIE";
++			};
++
++			/* adafruit 1.8" TFT prototype cape */
++			slot@8 {
++				ti,cape-override;
++				compatible = "kernel-command-line", "runtime";
++				board-name = "Bone-TFT";
++				version = "00A0";
++				manufacturer = "Adafruit";
++				part-number = "BB-BONE-TFT-01";
++			};
++
++			/* adafruit RTC DS1307 prototype cape */
++			slot@9 {
++				ti,cape-override;
++				compatible = "kernel-command-line", "runtime";
++				board-name = "Bone-RTC";
++				version = "00A0";
++				manufacturer = "Adafruit";
++				part-number = "BB-BONE-RTC-01";
++			};
++
++			slot@10 {
++				ti,cape-override;
++				compatible = "kernel-command-line", "runtime";
++				board-name = "Bone-Hexy";
++				version = "00A0";
++				manufacturer = "Koen Kooi";
++				part-number = "BB-BONE-HEXY-01";
++			};
++			/* MRF24J40 Cape Override */
++			slot@11 {
++				ti,cape-override;
++				compatible = "kernel-command-line", "runtime";
++				board-name = "Bone-MRF24J40";
++				version = "00A0";
++				manufacturer = "Signal 11 Software";
++				part-number = "BB-BONE-MRF24J40";
++			};
++
++			/* RS232 cape */
++			slot@12 {
++				ti,cape-override;
++				compatible = "kernel-command-line", "runtime";
++				board-name = "BB-BONE-RS232";
++				version = "00A0";
++				manufacturer = "Adafruit";
++				part-number = "BB-BONE-RS232-01";
++			};
++
++			/* GPS cape */
++			slot@13 {
++				compatible = "kernel-command-line", "runtime";
++				board-name = "BB-BONE-GPS";
++				version = "00A0";
++				manufacturer = "Adafruit";
++				part-number = "BB-BONE-GPS-01";
++			};
++
++		};
++
++		/* mapping between board names and dtb objects */
++		capemaps {
++			/* DVI cape */
++			cape@0 {
++				/* board-name = "BeagleBone DVI-D CAPE"; */
++				part-number = "BB-BONE-DVID-01";
++				version@00A0 {
++					version = "00A0";
++					dtbo = "cape-bone-dvi-00A0.dtbo";
++				};
++				version@00A1 {
++					version = "00A1", "01";
++					dtbo = "cape-bone-dvi-00A1.dtbo";
++				};
++				version@00A2 {
++					version = "00A2", "A2";
++					dtbo = "cape-bone-dvi-00A2.dtbo";
++				};
++				version@00A3 {
++					version = "00A3";
++					dtbo = "cape-bone-dvi-00A2.dtbo";
++				};
++			};
++
++			/* geiger cape */
++			cape@1 {
++				part-number = "BB-BONE-GEIGER";
++				version@00A0 {
++					version = "00A0";
++					dtbo = "cape-bone-geiger-00A0.dtbo";
++				};
++			};
++
++			/* LCD3 cape */
++			cape@2 {
++				part-number = "BB-BONE-LCD3-01";
++				version@00A0 {
++					version = "00A0";
++					dtbo = "cape-bone-lcd3-00A0.dtbo";
++				};
++				version@00A2 {
++					version = "00A2";
++					dtbo = "cape-bone-lcd3-00A2.dtbo";
++				};
++			};
++
++			/* Weather cape */
++			cape@3 {
++				part-number = "BB-BONE-WTHR-01";
++				version@00A0 {
++					version = "00A0";
++					dtbo = "cape-bone-weather-00A0.dtbo";
++				};
++				version@00B0 {
++					version = "00B0";
++					dtbo = "cape-bone-weather-00B0.dtbo";
++				};
++			};
++
++			/* nixie cape */
++			cape@4 {
++				part-number = "BB-BONE-NIXIE";
++				version@00A0 {
++					version = "00A0";
++					dtbo = "cape-bone-nixie-00A0.dtbo";
++				};
++			};
++			cape@5 {
++				part-number = "BB-BONE-TFT-01";
++				version@00A0 {
++					version = "00A0";
++					dtbo = "cape-bone-adafruit-lcd-00A0.dtbo";
++				};
++			};
++
++			cape@6 {
++				part-number = "BB-BONE-RTC-01";
++				version@00A0 {
++					version = "00A0";
++					dtbo = "BB-BONE-RTC-00A0.dtbo";
++				};
++			};
++
++			cape@7 {
++				part-number = "BB-BONE-HEXY-01";
++				version@00A0 {
++					version = "00A0";
++					dtbo = "cape-bone-hexy-00A0.dtbo";
++				};
++			};
++			/* mrf24j40 cape */
++			cape@8 {
++				part-number = "BB-BONE-MRF24J40";
++				version@00A0 {
++					version = "00A0";
++					dtbo = "cape-bone-mrf24j40-00A0.dtbo";
++				};
++			};
++			/* expansion test */
++			cape@9 {
++				part-number = "BB-BONE-EXPTEST";
++				version@00A0 {
++					version = "00A0";
++					dtbo = "cape-bone-exptest-00A0.dtbo";
++				};
++			};
++			cape@10 {
++				part-number = "BB-BONE-RS232-01";
++				version@00A0 {
++					version = "00A0";
++					dtbo = "BB-BONE-RS232-00A0.dtbo";
++				};
++			};
++
++			cape@11 {
++				part-number = "BB-BONE-GPS-01";
++				version@00A0 {
++					version = "00A0";
++					dtbo = "BB-BONE-GPS-00A0.dtbo";
++				};
++			};
++
++
++			/* beaglebone black hdmi on board (No audio) */
++			cape@12 {
++				part-number = "BB-BONELT-HDMIN";
++				version@00A0 {
++					version = "00A0";
++					dtbo = "cape-boneblack-hdmin-00A0.dtbo";
++				};
++			};
++
++			/* remain backwards compatible with old EEPROM */
++			cape@13 {
++				part-number = "2191";
++				version@R2 {
++					version = "R2";
++					dtbo = "cape-bebopr-R2.dtbo";
++				};
++			};
++
++			/* LOGIBONE cape */
++			cape@14 {
++				part-number = "BB-BONE-LOGIBONE";
++				version@00R1 {
++					version = "00R1";
++					dtbo = "BB-BONE-LOGIBONE-00R1.dtbo";
++				};
++			};
++
++		};
++	};
++
++	vmmcsd_fixed: fixedregulator@0 {
++		compatible = "regulator-fixed";
++		regulator-name = "vmmcsd_fixed";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++	};
++
++};
++
++&i2c0 {
++	status = "okay";
++	clock-frequency = <400000>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2c0_pins>;
++
++	tps: tps@24 {
++		reg = <0x24>;
++	};
++
++	baseboard_eeprom: baseboard_eeprom@50 {
++		compatible = "at,24c256";
++		reg = <0x50>;
++	};
++};
++
++&i2c2 {
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2c2_pins>;
++
++	clock-frequency = <100000>;
++
++	cape_eeprom0: cape_eeprom0@54 {
++		compatible = "at,24c256";
++		reg = <0x54>;
++	};
++
++	cape_eeprom1: cape_eeprom1@55 {
++		compatible = "at,24c256";
++		reg = <0x55>;
++	};
++
++	cape_eeprom2: cape_eeprom2@56 {
++		compatible = "at,24c256";
++		reg = <0x56>;
++	};
++
++	cape_eeprom3: cape_eeprom3@57 {
++		compatible = "at,24c256";
++		reg = <0x57>;
++	};
++};
++
++/include/ "tps65217.dtsi"
++
++&tps {
++	ti,pmic-shutdown-controller;
++
++	interrupt-parent = <&intc>;
++	interrupts = <7>;	/* NNMI */
++
++	regulators {
++		dcdc1_reg: regulator@0 {
++			regulator-always-on;
++		};
++
++		dcdc2_reg: regulator@1 {
++			/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
++			regulator-name = "vdd_mpu";
++			regulator-min-microvolt = <925000>;
++			regulator-max-microvolt = <1325000>;
++			regulator-boot-on;
++			regulator-always-on;
++		};
++
++		dcdc3_reg: regulator@2 {
++			/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
++			regulator-name = "vdd_core";
++			regulator-min-microvolt = <925000>;
++			regulator-max-microvolt = <1150000>;
++			regulator-boot-on;
++			regulator-always-on;
++		};
++
++		ldo1_reg: regulator@3 {
++			regulator-always-on;
++		};
++
++		ldo2_reg: regulator@4 {
++			regulator-always-on;
++		};
++
++		ldo3_reg: regulator@5 {
++			regulator-min-microvolt = <1800000>;
++			regulator-max-microvolt = <3300000>;
++			regulator-always-on;
++		};
++
++		ldo4_reg: regulator@6 {
++			regulator-always-on;
++		};
++	};
++
++};
++
++&cpsw_emac0 {
++	phy_id = <&davinci_mdio>, <0>;
++};
++
++&cpsw_emac1 {
++	phy_id = <&davinci_mdio>, <1>;
++};
++
++&mmc1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&mmc1_pins>;
++	bus-width = <0x4>;
++	cd-gpios = <&gpio1 6 0>; /* gpio1 is misnamed, 0 == GPIO_ACTIVE_HIGH */
++	cd-inverted;
++	status = "okay";
++	vmmc-supply = <&ldo3_reg>;
++	ti,vcc-aux-disable-is-sleep;
++};
++
++&edma {
++	ti,edma-xbar-event-map = <32 12>,	/* gpevt2 -> 12 */
++				 <30 20>;	/* xdma_event_intr2 -> 20 */
++};
++
++&sham {
++	status = "okay";
++};
++
++&aes {
++	status = "okay";
++};
++
++&usb_otg_hs {
++	interface_type = <1>;
++	power = <250>;
++	status = "okay";
++};
++
++&mmc1 {
++	vmmc-supply = <&vmmcsd_fixed>;
++};
++
++&cpu {
++	/*
++	 * To consider voltage drop between PMIC and SoC,
++	 * tolerance value is reduced to 2% from 4% and
++	 * voltage value is increased as a precaution.
++	 */
++	operating-points = <
++		/* kHz    uV */
++		1000000	1350000
++		800000	1300000
++		600000  1112000
++		300000   969000
++	>;
++};
++
++&gpmc {
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&nandflash_pins_s0>;
++	ranges = <0 0 0x08000000 0x10000000>;   /* CS0: NAND */
++	nand@0,0 {
++		reg = <0 0 0>; /* CS0, offset 0 */
++		nand-bus-width = <8>;
++		ti,nand-ecc-opt = "bch8";
++		gpmc,device-nand = "true";
++		gpmc,device-width = <1>;
++		gpmc,sync-clk-ps = <0>;
++		gpmc,cs-on-ns = <0>;
++		gpmc,cs-rd-off-ns = <44>;
++		gpmc,cs-wr-off-ns = <44>;
++		gpmc,adv-on-ns = <6>;
++		gpmc,adv-rd-off-ns = <34>;
++		gpmc,adv-wr-off-ns = <44>;
++		gpmc,we-on-ns = <0>;
++		gpmc,we-off-ns = <40>;
++		gpmc,oe-on-ns = <0>;
++		gpmc,oe-off-ns = <54>;
++		gpmc,access-ns = <64>;
++		gpmc,rd-cycle-ns = <82>;
++		gpmc,wr-cycle-ns = <82>;
++		gpmc,wait-on-read = "true";
++		gpmc,wait-on-write = "true";
++		gpmc,bus-turnaround-ns = <0>;
++		gpmc,cycle2cycle-delay-ns = <0>;
++		gpmc,clk-activation-ns = <0>;
++		gpmc,wait-monitoring-ns = <0>;
++		gpmc,wr-access-ns = <40>;
++		gpmc,wr-data-mux-bus-ns = <0>;
++
++		#address-cells = <1>;
++		#size-cells = <1>;
++		elm_id = <&elm>;
++
++		/* MTD partition table */
++		partition@0 {
++			label = "SPL";
++			reg = <0x00000000 0x000020000>;
++		};
++
++		partition@1 {
++			label = "SPL.backup1";
++			reg = <0x00020000 0x00020000>;
++		};
++
++		partition@2 {
++			label = "SPL.backup2";
++			reg = <0x00040000 0x00020000>;
++		};
++
++		partition@3 {
++			label = "SPL.backup3";
++			reg = <0x00060000 0x00020000>;
++		};
++
++		partition@4 {
++			label = "u-boot";
++			reg = <0x00080000 0x00080000>;
++		};
++
++		partition@5 {
++			label = "u-boot-spl-os";
++			reg = <0x00100000 0x00020000>;
++		};
++
++		partition@6 {
++			label = "u-boot-env";
++			reg = <0x00120000 0x00020000>;
++		};
++
++		partition@7 {
++			label = "kernel";
++			reg = <0x00280000 0x00500000>;
++		};
++
++		partition@8 {
++			label = "rootfs";
++			reg = <0x00780000 0x1F880000>;
++		};
++	};
++};
++
